1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and more particularly to a method for optimizing semiconductor processing.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g. transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender non-optimal control of critical processing parameters, such as throughput accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance. An ideal monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
Among the parameters that would be useful to monitor and control are the temperatures and lamp power levels that silicon wafers are exposed to during rapid thermal processing (RTP) used to activate dopant implants, for example. An RTP chamber heats up during successive wafer processing so that the thermal environment experienced by early wafers will be different from the thermal environment experienced by later wafers. For example, if the RTP chamber is not preheated, the first wafers will be run in a colder RTP chamber than later wafers. This will cause differences in wafer processing within a lot of wafers, leading to decreased satisfactory wafer throughput, decreased reliability, decreased precision and decreased accuracy in the semiconductor manufacturing.
Sub-optimal preheating may also be problematic. For example, a manufacturer of rapid thermal annealing (RTA) tool provides a quartz tube temperature reading to the tool user to better understand the process conditions, and states that by preheating the tool (with a recipe similar to the production recipe) to a set tube temperature, the tube temperature traces from the 1.sup.st workpiece can be made to overlap the 2.sup.nd through 25.sup.th workpieces, and, thus the system is properly preheated. From experiments and data we have produced, this preheat was found to be insufficient and sub-optimal. The 1.sup.st workpiece was receiving more of an anneal (a higher temperature due to a higher amount of incident lamp radiation) than the rest of the lot (a "1.sup.st workpiece effect"). This again will cause differences in wafer processing within a lot of wafers, leading to decreased wafer reliability and decreased processing precision and accuracy.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.